Novel high-speed architecture for machine vision applications
Farroha, Bassam S.
Deshmukh, Raghvendra G.
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This paper focuses on producing a state-of-the-art technique for designing an image recognition system for machine vision applications. The motivation behind the new system design is to provide a unique methodology, using strategic design techniques, to implement a system that addresses real-world image recognition applications. The introduction of application-specific, massively parallel array of processors, where low-level processing is accomplished on reconfigurable hardware structures, highlights the scheme. The system was built and simulated on a VLSI chip and results were verified using Electric Rules Check and Harris Timing Analysis examination tools. The system is composed of there functional layers and a main control unit. The top two layers are used for image loading and manipulation and the third layer is used for processing the pixel values. Each layer has a local control unit, while the main control unit oversees the operations of the whole system and synchronizes the processes. A CAD designer tool was implemented to facilitate the design and reconfiguration f the low-level processing elements. This tool has a modular library of processing elements and a logic verification algorithm. The current architecture of the chip was built to accommodate a 64 by 64 array with unlimited stackable characteristics to handle larger images. This paper will present the top level design layers, the distributed control, and demonstrate that the proposed system is image complexity invariant. The massively parallel approach of transferring data and control signals and the processing of image data is presented. The system takes into consideration cost, size, speed,and reliability needs of today's applications. ©2005 Copyright SPIE - The International Society for Optical Engineering.